1. Field
This relates generally to the manufacturing of semiconductor devices and, more specifically, to methods for plasma doping a non-planar semiconductor device.
2. Related Art
As semiconductor manufacturers continue to shrink the dimensions of transistor devices in order to achieve greater circuit density and higher performance, short-channel effects, such as parasitic capacitance and off-state leakage, increasingly impair transistor device characteristics. Fin field effect transistors (FinFETs), such as double-gate transistors, tri-gate transistors, and gate-all-around transistors, are a recent development in semiconductor processing for controlling such short-channel effects. A FinFET has a fin that protrudes above a substrate surface. The fin creates a longer effective channel length, thereby reducing short channel effects.
The fin defines the channel, the source/drain regions, and the source/drain extension regions of the FinFET. Like conventional planar metal-oxide semiconductor field effect transistors (MOSFETs), the channel, source/drain regions, and source/drain extension regions of a FinFET device are doped with impurities (i.e., dopants) to produce desired electrical characteristics. Ideally, these regions are each uniformly doped along the height of the fin. Poor dopant uniformity may cause undesirable threshold voltage variations across the height of the gate as well as source/drain punch-through issues.
Plasma doping (also known as plasma immersion ion implanting) is one method for doping the channel, source/drain, and source/drain extension regions of a FinFET device. However, achieving a uniform dopant profile across the height of the fin may be challenging using plasma doping. The plasma sheath formed during plasma doping may be very large relative to the dimensions of the fins and thus the plasma sheath may not conform to the fin. As a result, plasma doping may occur mainly in the vertical direction where the top of the fin may be more heavily doped than the bottom of the fin.